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How To Avoid Pits And Leaks On The Design Side Of PCB Boards!

May 10, 2023

How To Avoid Pits And Leaks On The Design Side Of PCB Boards!

The design of electronic products is from drawing schematic diagrams to PCB layout and wiring. Due to a lack of knowledge in this area of work experience, various mistakes often occur, hindering our follow-up work, and in severe cases, the circuit boards made cannot be used at all. Therefore, we should try our best to improve our knowledge in this area and avoid all kinds of mistakes.


This article introduces the common drilling problems when PCB drawing boards are used, so as to avoid stepping on the same pits in the future. Drilling is divided into three categories, through the hole, blind hole, and buried hole. Through holes include plug-in holes (PTH), screw positioning holes (NPTH), blind, buried holes, and via holes (VIA) through holes, all of which play the role of multi-layer electrical conduction. Regardless of the type of hole, the consequence of the problem of missing holes is that the entire batch of products cannot be used directly. Therefore, the correctness of the drilling design is particularly important.


Case Explanation of Pits And Leaks On The Design Side Of PCB Boards

Problem 1: The Altium-designed file slots are misplaced;


Description of the problem: The slot is missing, and the product cannot be used.


Reason analysis: The design engineer missed the slot for the USB device when making the package. When he found this problem when drawing the board, he did not modify the package, but directly drew the slot on the hole symbol layer. In theory, there is no big problem with this operation, but in the manufacturing process, only the drilling layer is used for drilling, so it is easy to ignore the existence of slots in other layers, resulting in the missed drilling of this slot, and the product cannot be used. Please see the picture below;


How to avoid pits: Each layer of the OEM PCB design file has the function of each layer. Drill holes and slot holes must be placed in the drill layer, and it cannot be considered that the design can be manufactured.


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Question 2: Altium-designed file via hole 0 D code;


Description of the problem: The leakage is open and non-conductive.


Cause analysis: Please see Figure 1, there is a leak in the design file, and the leak is indicated during the DFM manufacturability check. After checking the cause of the leak, the diameter of the hole in the Altium software is 0, resulting in no holes in the design file, see Figure 2.

The reason for this leakage hole is that the design engineer made a mistake when drilling the hole. If the problem of this leakage hole is not checked, it is difficult to find the leakage hole in the design file. The leakage hole directly affects the electrical failure and the designed product cannot be used.


How to avoid pits: DFM manufacturability testing must be carried out after the circuit diagram design is completed. The leaked vias cannot be found in manufacturing and production during design. DFM manufacturability testing before manufacturing can avoid this problem.


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Figure 1: Design file leak


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Figure 2: Altium aperture is 0


Question 3: The file vias designed by PADS cannot be output;


Description of the problem: The leakage is open and non-conductive.


Cause Analysis: Please see Figure 1, when using DFM manufacturability testing, it indicates many leaks. After checking the cause of the leakage problem, one of the vias in PADS was designed as a semi-conducting hole, resulting in the design file not outputting the semi-conducting hole, resulting in a leak, see Figure 2.


Double-sided panels do not have semi-conducting holes. Engineers mistakenly set via holes as semi-conducting holes during design, and output semi-conducting holes are leaked during output drilling, resulting in leaky holes.


How to avoid pits: This kind of misoperation is not easy to find. After the design is completed, it is necessary to conduct DFM manufacturability analysis and inspection and find problems before manufacturing to avoid leakage problems.


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Figure 1: Design file leak


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Figure 2: PADS software double-panel vias are semi-conducting vias